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16-bit, 200 msps/250 msps analog-to-digital converter preliminary technical data AD9467 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features 75.5 dbfs snr to 170 mhz at 250 msps @ 2.5 v p-p fs 74 dbfs snr to 170 mhz at 250 msps @ 2.0 v p-p fs 90 dbfs sfdr to 300 mhz at 250 msps (@ ?1 dbfs) at 2.5 v p-p fs 95 dbfs sfdr to 170 mhz at 250 msps (@ ?1 dbfs) at 2.0 v p-p fs 100 dbfs sfdr at 100 mhz at 160 msps (@ ?1 dbfs) 60 fs rms jitter excellent linearity dnl = 1.0 lsb typical inl = 3.0 lsb typical 2 v p-p to 2.5 v p-p (default) differential full-scale input (programmable) integrated input buffer external reference support option clock duty cycle stabilizer output clock available serial port control built-in selectable digital test pattern generation selectable output data format lvds outputs (ansi-644 compatible) 1.8 v and 3.3 v supply operation applications multicarrier, multimode cellular receivers antenna array positioning power amplifier linearization broadband wireless radar infrared imaging communications instrumentation general description the AD9467 is a 16-bit, monolithic, if sampling analog-to- digital converter (adc). it is optimized for high performance over wide bandwidths and ease of use. the product operates at a 250 msps conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range. the adc requires 1.8 v and 3.3 v power supplies and a low voltage differential input clock for full performance operation. no external reference or driver components are required for functional block diagram 16 2 16 2 pipeline adc clock and timing management ref lvds output staging a vdd1 a gnd drvdd drgnd a vdd2 avdd3 spivdd xvref AD9467 buffer vin+ clk+ clk? vin? csb sdio sclk or+/or? d15+/d15? to d0+/d0? dco+/dco? 09029-001 figure 1. many applications. data outputs are lvds compatible (ansi-644 compatible) and include the means to reduce the overall current needed for short trace distances. a data clock output (dco) for capturing data on the output is provided for signaling a new output bit. the internal power-down feature supported via the spi and typically consumes less than 5 mw when disabled. optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. the AD9467 is available in a pb-free, 72-lead, lfcsp specified over the ?40c to +85c industrial temperature range. product highlights 1. if optimization capability used to improve sfdr. 2. outstanding sfdr performance for if sampling applications such as multicarrier, multimode 3g, and 4g cellular base station receivers. 3. ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture. 4. packaged in a pb-free, 72-lead lfcsp package. 5. clock duty cycle stabilizer (dcs) maintains overall adc performance over a wide range of input clock pulse widths. 6. standard serial port interface (spi) supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock dcs. datasheet.in
AD9467 preliminary technical data rev. prb | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac specifications .......................................................................... 4 ? digital specifications ................................................................... 5 ? switching specifications .............................................................. 6 ? timing diagrams .............................................................................. 6 ? absolute maximum ratings ............................................................ 7 ? thermal impedance ..................................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ..............................8 ? equivalent circuits ......................................................................... 10 ? theory of operation ...................................................................... 11 ? analog input considerations ................................................... 11 ? clock input considerations ...................................................... 13 ? serial port interface (spi) .............................................................. 17 ? hardware interface ..................................................................... 17 ? memory map .................................................................................. 19 ? reading the memory map table .............................................. 19 ? reserved locations .................................................................... 19 ? default values ............................................................................. 19 ? logic levels ................................................................................. 19 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 24 ? revision history datasheet.in
preliminary technical data AD9467 rev. prb | page 3 of 24 specifications avdd1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, drvdd = 1.8 v, specified maximum sampling rate, 2.5 v p-p differential input, 1.25 v internal reference, ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted. table 1. AD9467bcpz-200 AD9467bcpz-250 parameter 1 temp min typ max min typ max unit resolution 16 16 bits accuracy no missing codes full guaranteed guaranteed offset error full 1 1 lsb gain error full 3 3 %fsr differential nonlinearity (dnl) full 1 1 lsb integral nonlinearity (inl) full 3 3 lsb temperature drift offset error full tbd tbd ppm/c gain error full tbd tbd ppm/c analog inputs differential input voltage range (i nternal vref = 1 v to 1.25 v) full 2 2.5 2.5 2 2.5 2.5 v p-p common-mode voltage full 2.25 2.1 v differential input resistance full 530 530 differential input capacitanc e full 3.5 3.5 pf analog bandwidth 25c 900 900 mhz xvref input input voltage full 1 1.25 1 1.25 v input capacitance full 3 3 pf power supply avdd1 full 1.75 1.8 1. 85 1.75 1.8 1.85 v avdd2 full 3.0 3.3 3.6 3.0 3.3 3.6 v avdd3 full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v i avdd1 full 520 560 ma i avdd2 full 50 50 ma i avdd3 full 30 30 ma i drvdd full 45 45 ma total power dissipation (including output drivers) full 1.24 1.32 w power-down dissipation full 5 5 mw 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. datasheet.in
AD9467 preliminary technical data rev. prb | page 4 of 24 ac specifications avdd1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, drvdd = 1.8 v, specified maximum sampling rate, 2.5 v p-p differential input, 1.25 v internal reference, ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted. table 2. AD9467bcpz-200 AD9467bcpz-250 parameter 1 temp min typ max min typ max unit analog input full scale 2/2.5 2/2.5 v p-p signal-to-noise ratio (snr) f in = 5 mhz full 74.7/76.4 74.7/76.4 dbfs f in = 97 mhz full 74.5/76.1 74.5/76.1 dbfs f in = 140 mhz full 74.5/75.8 74.5/75.8 dbfs f in = 170 mhz full 74.3/75.6 74.3/75.6 dbfs f in = 210 mhz full 74/75.1 74/75.1 dbfs f in = 300 mhz full 73.3/74.4 73.3/74.4 dbfs signal-to-noise and distortion ratio (sinad) f in = 5 mhz full 74.6/76.3 74.6/76.3 dbfs f in = 97 mhz full 74.4/76 74.4/76 dbfs f in = 140 mhz full 74.3/75.6 74.3/75.6 dbfs f in = 170 mhz full 74.1/75.4 74.1/75.4 dbfs f in = 210 mhz full 73.7/74.8 73.7/74.8 dbfs f in = 300 mhz full 73/74.1 73/74.1 dbfs effective number of bits (enob) f in = 5 mhz full 12.1/12.4 12.1/12.4 bits f in = 97 mhz full 12.1/12.3 12.1/12.3 bits f in = 140 mhz full 12/12.2 12/12.2 bits f in = 170 mhz full 12/12.2 12/12.2 bits f in = 210 mhz full 11.9/12.1 11.9/12.1 bits f in = 300 mhz full 11.8/12 11.8/12 bits spurious-free dynamic range (sfdr), 2 nd or 3 rd hd f in = 5 mhz full 98/95 98/95 dbfs f in = 97 mhz full 96/92 96/92 dbfs f in = 140 mhz full 96/91 96/91 dbfs f in = 170 mhz full 95/90 95/90 dbfs f in = 210 mhz full 92/90 92/90 dbfs f in = 300 mhz full 92/90 92/90 dbfs worst other (excluding second or third) f in = 5 mhz full 98/98 98/98 dbfs f in = 97 mhz full 97/97 97/97 dbfs f in = 140 mhz full 97/97 97/97 dbfs f in = 170 mhz full 97/97 97/97 dbfs f in = 210 mhz full 97/97 97/97 dbfs f in = 300 mhz full 97/97 97/97 dbfs two-tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs f in1 = 97 mhz, f in2 = 98 mhz 25c tbd/tbd tbd/tbd dbc f in1 = 171 mhz, f in2 = 170 mhz 25c tbd/tbd tbd/tbd dbc 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. datasheet.in
preliminary technical data AD9467 rev. prb | page 5 of 24 digital specifications avdd1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, drvdd = 1.8 v, specified maximum sampling rate, 2.5 v p-p differential input, 1.25 v internal reference, ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted. table 3. AD9467bcpz-200 AD9467bcpz-250 parameter 1 temp min typ max min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl cmos/lvds/lvpecl differential input voltage 2 full 250 250 mv p-p input common-mode voltage full 0.8 0.8 v input resistance (differential) 25c 20 20 k input capacitance 25c 2.5 2.5 pf logic inputs (sclk, csb, sdio) logic 1 voltage full 1.2 3.6 1.2 3.6 v logic 0 voltage full 0.3 0.3 v input resistance 25c 30 30 k input capacitance 25c 0.5 0.5 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.7/3.1 1.7/3.1 v logic 0 voltage (i ol = 50 a) full 0.3 0.3 v digital outputs (d0+ to d15+, d0? to d15?, dco, or+, or?) logic compliance lvds lvds differential output voltage (v od ) full 247 545 247 545 mv output offset voltage (v os ) full 1.125 1.375 1.125 1.375 v output coding (default) offset binary offset binary 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 this is specified for lvds and lvpecl only. 3 this depends on if spivdd is tied to a 1.8 v or 3.3 v supply. datasheet.in
AD9467 preliminary technical data rev. prb | page 6 of 24 switching specifications avdd1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, drvdd = 1.8 v, specified maximum sampling rate, 2.5 v p-p differential input, 1.25 v internal reference, ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted. table 4. AD9467bcpz-200 AD9467bcpz-250 parameter 1 temp min typ max min typ max unit clock 2 maximum clock rate full 200 250 msps minimum clock rate full 10 10 msps clock pulse width high (t ch ) full 2.4 2 ns clock pulse width low (t cl ) full 2.4 2 ns output parameters 2, 3 propagation delay (t pd ) full 2.8 2.8 ns rise time (t r ) (20% to 80%) full 300 300 ps fall time (t f ) (20% to 80%) full 300 300 ps dco propagation delay (t cpd ) full 3 3 ns dco to data delay (t skew ) full 700 ?200 300 700 ?200 300 ps wake-up time (power-down) full 100 100 ms pipeline latency full 16 16 clock cycles aperture aperture delay (t a ) 25c 1.2 1.2 ns aperture uncertainty (jitter) 25c 60 60 fs rms out-of-range recovery time 25c 1 1 clock cycles 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 can be adjusted via the spi interface. 3 measurements were made using a part soldered to fr-4 material. timing diagrams 09029-002 n ? 1 n + 1 n + 2 n + 3 n + 4 n + 5 n t a t ch t cl 1/fs t skew t cpd t pd clk+ clk? dco+ dco? d14+/d15+ (msb) d14?/d15? (msb) d0+/d1+ (msb) d0?/d1? (msb) vin d15 d14 d15 d14 d15 d14 d15 d14 d15 d14 d15 d14 d1 d0 d1 d0 d1 d0 d1 d0 d1 d0 d1 d0 . . . figure 2. 16-bit output data timing datasheet.in
preliminary technical data AD9467 rev. prb | page 7 of 24 absolute maximum ratings table 5. parameter with respect to rating electrical avdd1, avdd3 agnd ?0.3 v to +2.0 v avdd2, spivdd agnd ?0.3 v to +3.9 v drvdd drgnd ?0.3 v to +2.0 v agnd drgnd ?0.3 v to +0.3 v avdd2, spivdd avdd1, avdd3 ?2.0 v to +3.9 v avdd1, avdd3 drvdd ?2.0 v to +2.0 v avdd2, spivdd drvdd ?2.0 v to +3.9 v digital outputs (dx+, dx?, or+, or?, dco+, dco?) drgnd ?0.3 v to drvdd+0.2 v clk+, clk? agnd ?0.3 v to avdd1+0.2 v vin+, vin? agnd ?0.3 v to avdd2+0.3 v xvref agnd ?0.3 v to avdd1+0.2 v sclk, csb, sdio agnd ?0.3 v to spivdd+0.2 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal impedance table 6. air flow velocity (m/sec) ja 1, 2 jb 1, 3, 4 jc 1, 5 unit 0.0 15.7c/w 7.5c/w 0.5 c/w 1.0 13.7c/w n/a n/a c/w 2.5 12.3c/w n/a n/a c/w 1 per jedec 51-7, plus jede c 51-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per jedec jesd51-8 (still air). 4 n/a = not applicable. 5 per mil-std 883, method 1012.1. esd caution datasheet.in
AD9467 preliminary technical data rev. prb | page 8 of 24 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 avdd1 avdd1 avdd1 avdd1 clk+ clk? avdd1 avdd1 avdd1 agnd avdd1 avdd1 avdd1 agnd avdd1 agnd 17 drgnd 18 drvdd 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 d1?/d0? d1+/d0+ d3?/d2? d3+/d2+ d5?/d4? d5+/d4+ d7?/d6? d7+/d6+ dco? dco+ d9?/d8? d9+/d8+ d11?/d10? d11+/d10+ d13?/d12? d13+/d12+ 35 d15?/d14? 36 d15+/d14+ 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 avdd1 avdd1 avdd1 spivdd csb sclk sdio dnc avdd1 agnd avdd3 agnd avdd3 agnd or+ or? drgnd drvdd notes 1. dnc = do not connect. 2. exposed thermal pad must be connected to agnd. 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 avdd1 avdd1 avdd1 avdd2 avdd2 vin? vin+ avdd2 avdd2 avdd1 avdd1 avdd1 avdd1 avdd1 avdd1 xvref avdd1 avdd1 09029-003 pin 1 indicator AD9467 top view (not to scale) figure 3. pin configuration, top view table 7. pin function descriptions pin no. mnemonic description 0 epad exposed paddle. the exposed paddle must be connected to agnd. 10, 14, 16, 41, 43, 45 agnd analog ground. 1, 2, 3, 4, 7, 8, 9, 11, 12, 13, 15, 46, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 70, 71, 72 avdd1 1.8 v analog supply. 64, 65, 68, 69 avdd2 3.3 v analog supply. 42, 44 avdd3 1.8 v analog supply. 51 spivdd 1.8 v or 3.3 v spi supply 17, 38 drgnd digital output driver ground. 18, 37 drvdd 1.8 v digital output driver supply. 67 vin? analog input complement. 66 vin+ analog input true. 6 clk? clock input complement. 5 clk+ clock input true. 19 d0?/d1? d0 (lsb) and d1 digital output complement. 20 d0+/d1+ d0 (lsb) and d1 true digital output true. 21 d2?/d3? d2 and d3 digital output complement. 22 d2+/d3+ d2 and d3 true digital output true. 23 d4?/d5? d4 and d5 digital output complement. 24 d4+/d5+ d4 and d5 true digital output true. 25 d6?/d7? d6 and d7 digital output complement. 26 d6+/d7+ d6 and d7 true digital output true. 29 d8?/d9? d8 and d9 digital output complement. 30 d8+/d9+ d8 and d9 true digital output true. 31 d10?/d11? d10 and d11 digital output complement. 32 d10+/d11+ d10 and d11 true digital output true. 33 d12?/d13? d12 and d13 digital output complement. 34 d12+/d13+ d12 and d13 true digital output true. 35 d14?/d15? d14 and d15 (msb) digital output complement. datasheet.in
preliminary technical data AD9467 rev. prb | page 9 of 24 pin no. mnemonic description 36 d14+/d15+ d14 and d15 (msb) true digital output true. 27 dco? data clock digital output complement. 28 dco+ data clock digital output true. 39 or? out-of-range digital output complement. 40 or+ out-of-range digital output true. 47 dnc do not connect (leave pin floating). 48 sdio serial data input/output. 49 sclk serial clock. 50 csb chip select bar. 57 xvref external vref option. datasheet.in
AD9467 preliminary technical data rev. prb | page 10 of 24 equivalent circuits v in+ avdd2 buf vin? avdd2 buf 265 ? 265 ? buf avdd2 v cml ~2.1v/2.25v 0 9029-004 figure 4. equivalent analog input circuit 0.8v 10k ? 12k ? 10k ? 10k ? clk+ clk? avdd1 09029-005 figure 5. equivalent clock input circuit dr v dd drgnd dx? dx+ v v v v 0 9029-007 figure 6. equivalent digital output circuit s clk, sdio and csb 30k ? 345 ? 09029-008 figure 7. equivalent sclk, sdio, and csb input circuit 09029-011 spivdd sdio figure 8. equivalent sdio output circuit 09029-109 1k ? 3pf x vref figure 9. equivalent external vref input circuit (when enabled) datasheet.in
preliminary technical data AD9467 rev. prb | page 11 of 24 theory of operation the AD9467 architecture consists of an input-buffered pipe- lined adc that consists of a 3-bit first stage, a 4-bit second stage, followed by four 3-bit stages and a final 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stage. the input buffer provides a linear high input impedance (for ease of drive) and isolates the adc driver from any kick-back due to the sample and hold operation. the buffer is optimized for high linearity, low noise, and low power. the quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate with a new input sample while the remain- ing stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched-capacitor dac and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. analog input considerations the analog input to the AD9467 is a differential buffer. for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common-mode settling errors are symmetrical. the analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades significantly if the analog input is driven with a single- ended signal. in either case, a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maxi- mum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low-pass filter at the input to limit unwanted broadband noise. see the an-742 application note, the an-827 application note, and the analog dialogue article transformer-coupled front-end for wideband a/d converters (volume 39, april 2005) for more information. in general, the precise values depend on the application. for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common-mode settling errors are symmetrical. these errors are reduced by the common-mode rejection of the adc. an internal reference buffer creates the positive and negative reference voltages, reft and refb, respectively, that define the span of the adc core. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the AD9467, the largest input span available is 2.5 v p-p. differential input configurations there are several ways to drive the AD9467 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. for applications where snr and sfdr are key parameters, differential transformer coupling is the recommended input configuration (see figure 10 and figure 11), because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9467. regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. using the adl5562 differential driver to drive the AD9467 provides excellent, flexible gain option to interface to the adc (see figure 13) for both baseband and high if applications. using an amplifier also provides better isolation from the preceding stages as well as better pass-band flatness. when using any amplifier, the user has the option to disconnect the input common-mode voltage buffer from the analog inputs. this allows the common-mode output pin of the amplifier to set this voltage between the interface of the two devices. see the memory map section for more details. ain+ ain? 3.5pf 530 ? adc internal input z AD9467 4.7pf 24 ? 24 ? 0.1 f 0.1f 0.1f 0.1f 33 ? 33 ? sma 33 ? 33 ? adt1-1wt 0.1f 0.1f adt1-1wt 10nh 0.1 f input z = 50 ? 0 9029-040 figure 10. differential transformer-coupled configuration for baseband applications up to 150 mhz datasheet.in
AD9467 preliminary technical data r e v. p r b | p a g e 12 o f 2 4 a i n + a i n ? 3 . 5 p f 5 3 0 ? ad c i n t e rna l i n pu t z a d 94 6 7 1 . 8 p f 2 0 ? 2 0 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 3 3 ? 3 3 ? sm a 1 5 ? 1 5 ? ad t 1 - 1 w t 0 . 1 f 0 . 1 f ad t 1 - 1 w t 1 0 n h 0 . 1 f i n pu t z = 5 0 ? 0 9 0 2 9 - 0 4 1 fi g ur e 1 1 . d i e r en t i a l t r an sf o r m er- c o upled c o n g u r a t i o n f o r if a pp l i c a t i o n s f r o m 1 5 0 t o 3 00 m h z fi g ur e 1 2 . d i e r en t i a l t r an sf o r m er- c o upled c o n g u r a t i o n f o r if a ppli c a t i o n s up t o 3 0 0 m h z fi g ur e 1 3 . d i e r en t i a l inpu t c o n g u r a t ion u s i ng t he ad l 5 5 6 2 tbd datasheet.in
preliminary technical data AD9467 rev. prb | page 13 of 24 clock input considerations for optimum performance, the AD9467 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this signal is typically ac-coupled to the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally and require no additional biasing. figure 14 shows a preferred method for clocking the AD9467. the low jitter clock source is converted from a single-ended signal to a differential signal using an rf transformer. the back-to- back schottky diodes across the secondary transformer limit clock excursions into the AD9467 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9467, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsm2812 50 ? 100 ? clk? clk+ adc xfmr 09029-056 mini-circuits ? adt1-1wt, 1:1 z clock input figure 14. transformer-coupled differential clock another option is to ac-couple a differential pecl or lvds signal to the sample clock input pins, as shown in figure 15 and figure 16. the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 / ad9520 / ad9522 family of clock drivers offers excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? 50 ? 1 50 ? 1 clk clk 1 50 ? resistors are optional. clk? clk+ adc 09029-057 pecl driver c lock input c lock input figure 15. differential pecl sample clock 100 ? 0.1f 0.1f 0.1f 0.1f 50 ? 1 lvds driver 50 ? 1 clk clk 1 50 ? resistors are optional. clk? clk+ adc 09029-058 c lock input c lock input figure 16. differential lvds sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9467 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the AD9467. when the dcs is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. however, some applications may require the dcs function to be off. if so, keep in mind that the dynamic range performance can be affected when operated in this mode. see the memory map section for more details on using this feature. the AD9467 contains a duty cycle stabilizer (dcs) that retimes the nonsampling, or falling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance. noise and distortion performanc e are nearly flat for a wide range of duty cycles when the dcs is on, any changes to the sampling frequency require several clock cycles to allow the internal timing to acquire and lock at the new sampling rate. clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated by snr = 20 log 10(2 f a t j ) in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 17). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9467. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs. datasheet.in
AD9467 preliminary technical data r e v. p r b | p a g e 14 o f 2 4 1 1 0 10 0 1 0 0 0 1 6 b i ts 1 4 b i ts 1 2 b i ts 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 1 1 0 12 0 13 0 0 . 125 p s 0 . 2 5 p s 0 . 5 p s 1 . 0 p s 2 . 0 p s a n a l o g i n p u t f re q u e n c y ( m h z) 10 b i t s 8 b i t s r m s c l o ck j i t t e r r e q u i r e m e n t s n r ( d b ) 0 9 0 2 9 - 0 6 1 f i gure 1 7 . i d ea l snr vs. input frequency a nd j i tter power dissipation and power-down mode a s sho w n in f i g ur e 18, th e p o wer dis si p a t ed b y th e AD9467 is pro p o r t i o n a l t o i t s s a m p le r a t e . e d i g i t a l p o w er d i s s i p a t i o n doe s n o t v a r y m u c h be c a u s e i t i s de t e r m i n e d p r i m a r i l y b y t h e d r v d d s u p p l y an d b i as c u r r e n t o f t h e l v ds o u t pu t d r i v er s. figure 1 8 . supp ly c urre nt v s . f s a mpl e f o r f i n = 5 mh z , ad 9 46 7 - 20 0 figure 1 9 . supp ly c urre nt v s . f s a mpl e f o r f i n = 5 mh z , ad 9 46 7 - 25 0 b y as s er t in g t h e p o w er - do wn op tio n via t h e s pi r eg i s t er ma p (0x08[1:0]), t h e AD9467 is p la c ed i n t o p o we r - d o wn m o d e . i n t hi s s t a te , t h e a dc t y p i c a l l y di s s i p a t e s 5 m w . d u r i n g p o w e r - d o w n , t h e l v ds o u t p ut d r i v ers a r e pla ce d i n a hig h i m p e dan c e s t a t e . i n p o w er - d o wn m o de , l o w p o we r d iss i p a t i o n is ac h i e v e d b y s h ut t i n g d o w n t h e i n t er n a l r ef er en c e , r ef er en c e b u er , di g i t a l o u t p ut, a n d b i a s i n g n e t w o r k s. e d e vi c e r e q u ires a pp r o x - ima t e l y 100 m s t o r es t o r e fu l l o p era t ion. s e e t h e m e m o r y m a p s e c t ion fo r m or e det a i ls o n usin g t h es e f e a t ur es . power supplies t o a c hie v e t h e be s t d y n a m i c p e r f o r ma n c e o f t h e AD9467 , i t i s r e c o m m e n d e d t h a t e a ch p o w e r s up p l y p i n b e d e c o u p l e d as cl o s e l y t o t h e p a c k a g e a s po s s i b l e w i t h 0 . 1 f , x 7 r o r x 5 r t y p e d e c o up l i n g c a p a c i t o r s . f o r o p t i m u m p e r f o r man c e , a l l s u p p l i e s sho ul d b e a t ty p i cal va l u e s o r s l i g h t l y hi g h er t o acc o m m o d a t e e l e v a t e d t e m p er a t u r e d r is, w h ich de p e nd o n t h e a pp l ic a t i o n. reference options e us e o f a n e x t er n al r efer en c e ma y b e n e ces s a r y t o enha n c e t h e gain a c c ura c y o f t h e ad c o r t o im p r o v e g a in m a t c h i n g w h en us i n g m u l t i p l e a d cs. e i n t er n al r efer en c e ca n b e e n a b le d v i a t h e sp i, al lo win g t h e us e o f a n ext er n al r efer en c e . s e e t h e m e m o r y m a p s e c t ion fo r m o r e det a i ls. e ext er n al r efer en c e is lo ade d b y t h e i n p u t o f a n in t er n a l b u er a m pli er ha vi n g 3 pf o f ca p a ci t a n c e t o g r o und . er e is als o a 1 k in t er n al r esis t o r in s er i es w i t h t h e i n pu t o f t h a t b u er . e ext er n al r efer ence m us t b e l i mi te d t o a no minal 1.25 v f o r a n in pu t fu l l-s c a le s w in g o f 2.5 v p-p . a d di t i o n al c a p a c i t a n c e m a y b e n e ces s a r y t o k e ep t h is p i n q u iet de p e nd i ng o n t h e ext er n al r efer en c e us e d . wh en n o t usi n g t h e x vre f p i n , i t c an b e t i e d t o g r o un d o r i s i n t er na l l y p u l le d t o g r o un d . h o w e v er , k e ep t h i s p i n q u iet r eg ar d les s. digital out puts an d timing e ad946 7 d i e r e n tial o u t pu t s c o n f o r m t o t h e an s i-64 4 l v ds s t and a r d o n de f a u l t p o w er - u p . e l v ds d r i v e r c ur r e n t is de r i v e d on ch i p a nd s e ts t h e o u t pu t c ur r e n t a t e ach o u t pu t e q u a l t o a no mina l 3 . 5 ma. a 1 0 0 di e r e n tial te r m in a t i o n r es i s t o r p laced a t t h e l v ds r e cei v er in p u ts r es u l t s in a no minal 350 mv swi n g a t t h e r e c ei v er . e AD9467 l vds o u t pu t s f a cili t a t e in ter f acin g wi t h l vds r e ce i v e r s in cu s t o m a si c s an d fpg a s f o r s u p er i o r sw i t c hi n g p er f o r m a n c e i n no i sy en v i ro nm en t s. si n g le p o i n t - t o - p o i n t n e t t o p o log i es a r e r e co mmen d e d wi th a 100 t er m ina t io n r esis t o r place d as clos e to t h e r e cei ver as p o s si b le . i f t h ere is n o fa r - e n d r e cei v er t er m ina t io n o r t h er e is p o o r di er en t i al t r ace r o u t ing, t im i n g er ro r s m a y r es u l t . t o a v o id s uc h t i m i n g e r ro r s, i t i s r e co mm e nde d t h a t t h e t r ac e lengt h b e n o lo n g er t h a n 12 i n ch es a nd t h a t t h e di er en t i al o u t pu t t r aces b e kep t cl o s e t o g et h er a nd a t e q ual len gt h s. an exa m ple o f t h e d c o and da t a w i t h p ro p er tr a c e l en gt h an d pos i t i o n i s s h o w n i n f i gu r e 20 . tbd tbd datasheet.in
preliminary technical data AD9467 r e v. p r b | p a g e 15 o f 2 4 figure 2 0 . output t i m i ng e x a m pl e in l v ds mode (def ault ), ad9 46 7 -2 50 f i gu r e 2 1 . output t i m i ng exa m pl e i n cmos m o de, ad946 7 -2 5 0 an exa m p le o f t h e l vds o u t pu t usin g the ans i -644 s t anda r d (def a u l t ) d a ta e y e a n d a ti m e i n t e r v a l e r r o r ( t i e ) j i t t er hi s t ogr a m w i t h tr a c e l e n g t h s l e s s t ha n 1 2 i n c h e s o n s t a n d a r d f r - 4 m a t er i a l i s s h o w n i n f i g u r e 22 . i t is t h e r es p o n s ib i li ty o f t h e us er t o det er - m i n e if t h e w a vef o r m s m e et t h e t i m i n g b u d g et o f t h e de s i g n . a dd i t i o n a l s p i o p ti on s a l l o w t h e u s er t o f ur t h er i n c r ea s e t h e i n t e r n a l d r ive c u r r e n t o f a l l ou t p u t s to d r ive longer t r a c e len gt h s, t h er e b y i n c r e a si n g timi n g m a r g i n ( s ee f i gur e 22 ). e s am e c a n b e d o n e w i t h sh o r te r t r a ces t o c on s e r ve o n d r vdd p o w er c on s u m p t i o n . e v e n th o u gh th i s p r od u c e s s h a r pe r r i s e a n d f a l l t i m e s o n t h e d a t a e d g e s a n d i s l e s s p ro n e t o bi t er ro r s, t h e p o w er diss i p a t i o n o f t h e d r vdd s upp l y i n c r ea s e s o r dec r e a ses d ep e nd - i n g o n h o w t hi s o p t i o n i s us e d . s e e t h e m e mo r y m a p s e c t i o n fo r mor e d et a i ls. figure 2 2 . d a ta e y e for lvds outputs in ansi-644 mod e with t r ace l e ngths le ss t h an 12 inc h e s on s t an d a rd f r - 4 , a d9 4 67 - 2 50 e f o r m a t o f t h e outpu t d a t a i s o s et b in a r y b y d ef a u l t . a n exa m ple o f t h e o u t p ut co din g fo r m a t can b e fo und i n t a b le 8. t o c h a n g e t h e o u t p u t d a t a f o r m a t t o t w o s c o m p lem e n t , s e e t h e m em o r y m a p s e c t i o n . ta b le 8. digit a l out p ut co d i ng code (v in+) ? (v in?), in pu t span = 2.5 v p-p (v) d i gital ou t pu t o set b i na ry (d15:d0 ) 65 , 5 36 +1 . 2 5 11 1 1 1 11 1 1 1 1 1 1 11 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 . 0 8 6 7 , 2 3 32 , 7 67 ?0 . 0 0 00 38 01 1 1 1 11 1 1 1 1 1 1 11 1 0 ?1 . 2 5 00 0 0 0 00 0 0 0 0 0 0 00 0 t w o o u t p u t c lo c ks a r e p r o v ide d t o as sis t in c a p t ur in g da t a f r o m th e AD9467. d a ta is c lo c k e d o u t o f th e AD9467 a nd m us t b e c a p t u r e d o n t h e r i s i n g a n d f a ll i n g e d g e s o f t h e d co t h a t s u p p o r t s d o u b le d a t a r a t e ( dd r) c a p t ur i n g. se e t h e t i m i n g d i a g r a m s h o w n i n f i gur e 2 f o r mor e in f o r m a t i o n . w h en t h e s p i is us e d , t h e d c o phas e can b e ad j us t e d i n 100ps e c in cr emen ts r ela t i v e t o t h e da ta e d g e . is en ab les t h e u s er t o r e n e s y s t em t i m i n g mar g i n s if r e q ui r e d . e de f a u l t d c o+ an d d c o? t i min g, as sh o w n in f i gur e 2, is 90 r e l a t i v e t o t h e outpu t d a t a e d ge . er e a r e 1 2 d i g i t a l o u t p ut t es t p a t t er n o p t i o n s a va i l ab l e t h a t c a n b e in i t i a t e d t h ro u g h t h e sp i . is is a u s e fu l f e a t u r e w h e n vali da t i n g r e ce iv er ca pt ur e an d t i min g. refer t o t a b le 10 fo r t h e outpu t bi t s e q ue n c i n g op t i o n s a va i la b le . s o m e t es t p a tt er n s h a v e t w o s er i a l s e q ue n t i a l w o r d s a n d c a n b e a l t er n a t e d i n va r i o us w a y s, d e p e nding o n t h e test p a tte r n c h o s en. n o te t h a t s o m e p a t t er ns ma y n o t ad h er e t o t h e da ta f o r m a t s e le c t o p tio n . e pn s e q ue n ce sh o r t p a t t er n p r o d uces a ps e udo ra n d om b i t s e q ue n c e t h a t r e p e a t s i t s e lf e v er y 2 9 ? 1 o r 511 b i ts. a des c r i p - tio n o f t h e pn s e q uence an d h o w i t is g e n era t e d ca n be f o u n d in s e c t io n 5.1 o f th e i t u-t 0.15 0 (05/96) s t a n da r d . e o n l y di er en ce is t h a t t h e s t a r t i n g va l ue m us t b e a s p e c i c val ue i n s t e ad o f al l 1 s (se e t a b le 9 f o r t h e i n i t i a l va l ue s) . tbd tbd tbd datasheet.in
AD9467 preliminary technical data rev. prb | page 16 of 24 the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 C 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu-t 0.150 (05/96) standard. the only differences are that the starting value must be a specific value instead of all 1s (see table 9 for the initial values) and the AD9467 inverts the bit stream with relation to the itu standard. table 9. pn sequence sequence initial value first three output samples (msb first) pn 9 sequence, short 0xffff 0x87be, 0xae64, 0x929d pn 23 sequence ,long 0x7fff 0x7e00, 0x807c, 0x801f consult the memory map section for information on how to change these additional digital output timing features through the spi. spi pins: sclk, sdio, csb for normal spi operation, these pins should be tied to agnd through a 100 k resistor on each pin. these pins are both 1.8 v and 3.3 v tolerant. however, the sdio output logic level is dependent on the bias of the spivdd pin. for 3.3 v logic, tie spivdd to 3.3 v (avdd2). for 1.8 v output logic, tie spivdd to 1.8 v (avdd1). the csb pin should be tied to avdd1 for applications that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. table 10. flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 0000 same yes 0010 +full-scale short 1111 1111 1111 1111 same yes 0011 ?full-scale short 0000 0000 0000 0000 same yes 0100 checkerboard 1010 1010 1010 1010 0101 0101 0101 0101 no 0101 pn sequence long 1 n/a n/a yes 0110 pn sequence short 1 n/a n/a yes 0111 one-/zero-word toggle 1111 1111 1111 1111 0000 0000 0000 0000 no 1 all test mode options except pn sequence short and pn sequence long can support 8- to 14-bit word lengths to verify data captu re to the receiver. datasheet.in
preliminary technical data AD9467 rev. prb | page 17 of 24 serial port interface (spi) the AD9467 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. this gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided down into fields, as detailed in the memory map section. detailed operational information can be found in the an-877 application note, interfacing to high speed adcs via spi . there are three pins that define the spi: sclk, sdio, and csb (see table 11). the sclk pin is used to synchronize the read and write data presented to the adc. the sdio pin is a dual- purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb pin is an active low control that enables or disables the read and write cycles. table 11. serial port pins pin function sclk serial clock. the serial shift clock input. sclk is used to synchronize serial interface reads and writes. sdio serial data input/ output. a dual-purpose pin. the typical role for this pin is an inp ut or output, depending on the instruction sent and the relative position in the timing frame. csb chip select bar (active low). this control gates the read and write cycles. the falling edge of the csb in conjunction with the rising edge of the sclk determines the start of the framing sequence. during an instruction phase, a 16-bit instruction is transmitted followed by one or more data bytes, which is determined by bit field w0 and bit field w1. an example of the serial timing and its definitions can be found in figure 24 and table 12. during normal operation, csb is used to signal to the device that spi commands are to be received and processed. when csb is brought low, the device processes sclk and sdio to process instructions. normally, csb remains low until the comm unication cycle is complete. however, if connected to a slow device, csb can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. csb can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until csb is taken high to end the communication cycle. this allows complete memory transfers without requiring additional instructions. regardless of the mode, if csb is taken high in the middle of a byte transfer, the spi state machin e is reset and the device waits for a new instruction. in addition to the operation mo des, the spi port configuration influences how the AD9467 operates . when operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. without an active csb line, streaming mode can be entered but not exited. in addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change from an input to an output at the appropriate point in the serial frame. data can be sent in msb- or lsb-first mode. msb-first mode is the default at power-up and can be changed by adjusting the configuration register. for more information about this and other features, see the an-877 application note, interfacing to high speed adcs via spi . hardware interface the pins described in table 11 compose the physical interface between the programming device of the user and the serial port of the AD9467. the sclk and csb pins function as inputs when using the spi. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. if multiple sdio pins share a common connection, care should be taken to ensure that proper v oh levels are met. assuming the same load for each AD9467, figure 23 shows the number of sdio pins that can be connected together and the resulting v oh level. 1.80 1.79 1.78 1.77 1.76 1.75 1.74 1.73 1.72 0 102030405060708090100 number of sdio pins connected together v oh (v) 09029-074 figure 23. sdio pin loading this interface is flexible enough to be controlled by either serial proms or pic mirocontrollers, providing the user with an alternative method, other than a full spi controller, to program the adc (see the an-812 application note). datasheet.in
AD9467 preliminary technical data rev. prb | page 18 of 24 don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t high t clk t low t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 09029-072 figure 24. serial timing details table 12. serial timing definitions parameter timing (minimum, ns) description t ds 5 setup time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 setup time between csb and sclk t h 2 hold time between csb and sclk t high 16 minimum period that sclk should be in a logic high state t low 16 minimum period that sclk should be in a logic low state t en_sdio 10 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 24) t dis_sdio 10 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 24) datasheet.in
preliminary technical data AD9467 rev. prb | page 19 of 24 memory map reading the memory map table each row in the memory map register table (see table 13) has eight address locations. the memory map is divided into three sections: the chip configuration register map (address 0x00 to address 0x02), the device index and transfer register map (address 0xff), and the adc functions register map (address 0x08 to address 0x107). the leftmost column of the memory map indicates the register address number, and the default value is shown in the second right- most column. the (msb) bit 7 column is the start of the default hexadecimal value given. for example, address 0x09, the clock register, has a default value of 0x01, meaning bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 0 of this address, the duty cycle stabilizer turns off. for more information on this and other functions, consult the an-877 application note, interfacing to high speed adcs via spi . reserved locations undefined memory locations should not be written to except when writing the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. default values when the AD9467 comes out of a reset, critical registers are preloaded with default values. these values are indicated in table 13, where an x refers to an undefined feature. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. datasheet.in
AD9467 preliminary technical data rev. prb | page 20 of 24 table 13. memory map register 1 addr. (hex) parameter name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) default notes/ comments chip configuration register 00 chip_port_config x lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 x x x 0x18 the nibbles should be mirrored so that lsb- or msb-first mode is set correctly regard- less of shift mode. 01 chip_id 8-bit chip id bits[7:0] (AD9467 = 0x50, default) read only default is unique chip id, different for each device. this is a read- only register. 02 chip_grade x child id [6:4] (identify device variants of chip id) 001 = 200 msps 010 = 250 msps x x x x read only child id used to differentiate graded devices. device index and transfer register ff device_update x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers data from the master shift register to the slave. adc functions 08 modes x x x x x x internal power- down mode 00 = chip run (default) 01 = full power- down 0x00 determines various generic modes of chip operation. 09 clock x x x x x x x duty cycle stabilizer 1 = on (default) 0 = off 0x01 turns the internal duty cycle stabilizer on and off. 0d test_io x x reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test modesee table 10 in the digital outputs and timing section 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checkerboard output 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = one-/zero-word toggle 0x00 when this register is set, the test data is placed on the output pins in place of normal data. 0f adc_input xvref 1 = on 0 = off (default) x x x x analog disconnect 1 = on 0 = off (default) x x 0x00 analog input functions 10 offset 8-bit digital offset adjustment 0000 0000 0000 0001 0000 0010 0000 0011 1111 1111 0x00 digital offset adjustment in lsbs. datasheet.in
preliminary technical data AD9467 rev. prb | page 21 of 24 addr. (hex) parameter name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) default notes/ comments 14 output_mode x 0 x digital output disable 1 = on 0 = off (default) 1 output invert 1 = on 0 = off (default) data format select 00 = offset binary (default) 01 = twos complement 10 = gray code 0x08 configures the outputs and the format of the data. 15 output_adjust x x x x coarse lvds adjust 0 = 3.5 ma (default) 1 = 2.0 ma output current drive adjust 000 = coarse adjust enabled 001 = 3.5 ma 010 = 3.25 ma 011 = 3.0 ma 100 = 2.75 ma 101 = 2.5 ma 110 = 2.25 ma 111 = 2.0 ma 0x00 determines lvds or other output properties. 16 output_phase dco output invert 1 = on 0 = off (default) x x x x x x x 0x00 determines digital clock output phase. 17 output_delay dco delay enable 1 = on 0 = off (default) x x 5-bit digital clock output delay adjustment 0 0000 0 0001 0 0010 0 0011 1 1111 0x00 determines digital clock output delay. 18 vref x x x x input full-scale range adjust 0000 = 2.0 v p-p 0110 = 2.1 v p-p 0111 = 2.2 v p-p 1000 = 2.3 v p-p 1001 = 2.4 v p-p 1010 = 2.5 v p-p (default) 0x0a 2c analog_input x x x x x input coupling mode 0 = ac coupling (default) 1 = dc coupling x x 0x00 determines the input coupling mode. 36 buffer current select 1 110101 = +530% 110100 = +520% 000010 = +20% 000001 = +10% 000000 = nominal (default) 111111 = -10% 111110 = -20% 110111 = -90% 110110 = -100% 1 0 0x02 determines the internal buffer current setting. 107 buffer current select 2 110101 = +530% 110100 = +520% 000010 = +20% 000001 = +10% 000000 = nominal (default) 111111 = -10% x x 0x03 determines the internal buffer current setting. datasheet.in
AD9467 preliminary technical data rev. prb | page 22 of 24 addr. (hex) parameter name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) default notes/ comments 111110 = -20% 110111 = -90% 110110 = -100% 1 x = dont care. datasheet.in
preliminary technical data AD9467 rev. prb | page 23 of 24 power and ground recommendations when connecting power to the AD9467 , it is recommended that three separate su pplies be used: one for analog av dd 1 ( 1.8 v) , one for analog avdd2 ( 3.3 v) and one for digital out put drivers drvdd (1.8 v) . if only one supply is available, it should be routed to the avdd 1 first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the drvdd. the user can employ several different decoupling capacitors to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts , with minimal trace lengths. a single pc board ground plane should be sufficient when using the AD9467 . with proper decoupling and smart parti - tioning of the pc boards analog, digital, and clock sections, optimum performance can be easily achieved. exposed paddle thermal heat slug recommendations it is required that the exposed paddle on the under side of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the AD9467 . an exposed continuous copper plane on the pcb should be con - nected to the AD9467 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be so lder- filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the conti nuous copper plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process , whereas using one continuous plane with no partitions only guarantees one tie point. see figure 25 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . silkscreen p artition pin 1 indic at or 09029-073 figure 25 . typical pcb layout datasheet.in
AD9467 preliminary technical data rev. prb | page 24 of 24 outline dimensions compliant to jedec standards mo-220-vnnd-4 121809-b 0.20 ref 0.90 0.85 0.80 0.70 0.65 0.60 0.05 max 0.01 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.60 8.50 sq 8.40 8.50 ref exposed pad (bottom view) top view 9.75 bsc sq 10.00 bsc sq pin 1 indicator seating plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indicator coplanarity 0.08 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min figure 26. 72-lead lead frame chip scale package, exposed pad [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp-72-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9467bcpz-250 C40c to +85c 72-lead lfcsp_vq cp-72-5 AD9467bcpz-200 C40c to +85c 72-lead lfcsp_vq cp-72-5 AD9467-200ebz AD9467-200 evaluation board AD9467-250ebz AD9467-250 evaluation board 1 z = rohs compliant part. ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr09029-0-8/10(prb) datasheet.in

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